1. Field of the Invention
The present invention relates to a multi-strobe circuit that generates a multi-phase strobe signal (multi-strobe signal) to evaluate levels of a signal, an evaluation target, at a plurality of edge timings of the multi-strobe signal.
2. Description of the Relate Art
A multi-strobe circuit is used in a test apparatus for testing semiconductor devices such as memories or DSPs (Digital Signal Processors). The multi-strobe circuit generates a multi-strobe signal (also referred to as a multi-phase strobe signal) having a plurality of edges in a single cycle period of a signal to be tested (for example, a binary digital signal), and determines levels of a signal outputted from a semiconductor device at each edge timing thereof. By using the multi-strobe circuit, a timing (change-point) at which a level of a signal outputted from a semiconductor device makes a transition, can be detected, allowing the circuit to be used in evaluating the semiconductor device.
FIG. 1 is a circuit diagram illustrating a structural example of a multi-strobe circuit 300. N pieces of first delay elements D11 to D1N (collectively referred to as a first delay element D1) are connected together in cascade. A signal S1 to be tested outputted from a DUT (Device UnderTest) is inputted to the first delay element D11 in a first stage, the signal S1 to be tested being provided with a predetermined delay Tpd when passing through each of the first delay element D1. That is, a signal S1i to be tested, which is delayed by i×Tpd in comparison with the signal S1 to be tested outputted from the DUT, is outputted from the first delay element D1i in the i-th stage.
Each of N pieces of second delay elements D21 to D2N (collectively referred to as a second delay element D2) is provided for each of N pieces of the first delay elements D11 to D1N, and connected together in cascade. A reference strobe signal STRB is inputted to the second delay element D21 in the first stage. The strobe signal STRB is provided with a predetermined delay (Tpd+Δt) when passing through each of the second delay element D2. The i-th phase strobe signal STRBi which is delayed by i×(Tpd+Δt) in comparison with the reference strobe signal STRB, is outputted from the second delay element D2 in the i-th stage.
Each of N pieces of latch circuits L1 to LN (also referred to as timing comparators) is also provided for each of N pieces of the first delay elements D11 to D1N. The i-th (where i is a natural number satisfying 1≦i≦N) latch circuit Li latches an output signal of the i-th first delay element D1i at an edge timing of the i-th phase strobe signal STRBi. It is needless to say that the latch circuit L1 illustrated by a D flip-flop in FIG. 1 can be replaced by various elements such as another flip-flop or latch circuit. Output signals SL1 to SLN of N pieces of the latch circuits L are inputted to a logic unit 310, which executes predetermined signal processing in accordance with evaluation items of the DUT. When the signal S1 to be tested makes a transition from 0 to 1 (or from 1 to 0) at an point, the output signals SL1 to SLN become thermometer codes in which 0 and 1 are varied with each other at a certain bit. Accordingly, the logic unit 310 includes a priority encoder.
A phase difference (timing) between the signal S1 to be tested to be inputted to the first delay element D1 and the strobe signal STRB to be inputted to the second delay element D2, is adjusted by a third delay element D3 provided in the preceding stage of N pieces of the second delay elements D2.
A relative time difference between the signal S1 to be tested and the strobe signal STRB is varied by Δt when passing through each of the first delay element D1 and the second delay element D2. That is, a value of the signal S1 to be tested can be determined at a timing of each of N pieces of the strobe signals (multi-strobe signals) STRB1 to STRBN, the phase between which is shifted by Δt from each other. Outline of the structure of the multi-strobe circuit 300 and performance thereof have been described above.
Because the multi-strobe circuit 300 includes a plurality of delay elements D1 and D2 and a plurality of latch circuits L, there is a problem that the circuit is large in size. In addition, if delay amounts of the first delay element D1 and the second delay element D2 are varied, timing accuracy between the signal S1 to be tested and the multi-strobe signals STRB1 to STRBN is deteriorated. In particular, as a resolution capacity Δt is smaller, variations in the delay amounts of the first delay element D1 and the second delay element D2 influence the above timing accuracy more significantly, resulting in a large skew.